The present disclosure relates to a semiconductor device, and more particularly to a multilayer semiconductor device in which a plurality of semiconductor devices are connected together via solder balls.
To further reduce the size of electronic equipments, it is important to increase the mounting density of a semiconductor device used for the electronic equipments. A mobile device such as mainly a portable phone includes a multilayer semiconductor device (package on package or POP) in which a plurality of semiconductor devices (a semiconductor package) are stacked, thereby realizing high density mounting of the semiconductor device.
As methods for fabricating a mounting structure in which a plurality of semiconductor devices are stacked on a printed board, there are pre-stacking and on-board stacking.
In pre-stacking, first, a plurality of semiconductor devices are individually fabricated, and then, a pass/fail determination is made for each of the semiconductor devices. Next, the semiconductor devices are stacked to form a multilayer semiconductor device, and then, the obtained multilayer semiconductor device is electrically connected to a printed board.
In on-board stacking, a plurality of semiconductor devices are sequentially mounted one by one on a printed board to form a multilayer semiconductor device on the printed board.
In general, in a semiconductor device, a semiconductor element is provided on an upper surface of an interconnect substrate using a flip-on-chip method, etc. and an external connection terminal is formed on a lower surface of the interconnection substrate. In general, a semiconductor device in which a plurality of external connection terminals are arranged in a lattice pattern on a lower surface of an interconnect substrate is called area array semiconductor device, and a semiconductor device in which external connection terminals are made of solder balls is called ball grid array (BGA) semiconductor device. To reduce the thickness of a mounting structure as small as possible, solder balls, etc. are arranged in part of an interconnect substrate located outside a semiconductor element.
In a BGA semiconductor device in which a semiconductor element is flip chip connected to an interconnect substrate, the thermal expansion coefficient is different between the semiconductor element and the interconnect substrate, and thus, the semiconductor device is warped during fabrication. Furthermore, the semiconductor device is warped more greatly as the thickness of the BGA semiconductor device is reduced.
If semiconductor devices are greatly warped, a large stress is applied to the semiconductor device when a multilayer semiconductor device is formed. Specifically, the stress is increased at solder joint portions which join stacked semiconductor devices, thus causing defective electrical conduction.
To solve the above-described problems, it has been discussed that a bonding area of a portion where an upper surface of an interconnect substrate of a lower semiconductor device and solder balls are bonded together is reduced to be smaller than that of a bonding area of a portion where a lower surface of an interconnect substrate of an upper semiconductor device and the solder balls are bonded together (see, for example, Japanese Patent Publication No. 2007-311643). In this manner, the bonding area can be set according to the magnitude of a stress applied thereto.